1. Field of the Invention
The present invention relates to methods of fabricating field emission arrays. Particularly, the present invention relates to field emission array fabrication methods wherein the emitter tips and their corresponding resistors are fabricated through a single mask. More particularly, the present invention relates to field emission array fabrication methods that employ only one mask to define the emitter tips and their corresponding resistors and that do not require a mask to define the column lines thereof.
2. Background of the Related Art
Typically, field emission displays (xe2x80x9cFEDsxe2x80x9d) include an array of pixels, each of which includes one or more substantially conical emitter tips. The array of pixels of a field emission display is typically referred to as a field emission array. Each of the emitter tips is electrically connected to a negative voltage source by means of a cathode conductor line, which is also typically referred to as a column line.
Another set of electrically conductive lines, which are typically referred to as row lines or as gate lines, extend over the pixels of the field emission array. Row lines typically extend across a field emission display substantially perpendicularly to the direction in which the column lines extend. Accordingly, the paths of a row line and of a column line typically cross proximate (above and below, respectively) the location of an emitter tip. The row lines of a field emission array are electrically connected to a relatively positive voltage source. Thus, as a voltage is applied across the column line and the row line, electrons are emitted by the emitter tips and accelerated through an opening in the row line.
As electrons are emitted by emitter tips and accelerate past the row line that extends over the pixel, the electrons are directed toward a corresponding pixel of a positively charged electro-luminescent panel of the field emission display, which is spaced apart from and substantially parallel to the field emission array. As electrons impact a pixel of the electro-luminescent panel, the pixel is illuminated. The degree to which the pixel is illuminated depends upon the number of electrons that impact the pixel.
Numerous techniques have been employed to fabricate field emission arrays and the resistors thereof. An exemplary field emission array fabrication technique includes fabricating the column lines and emitter tips prior to fabricating a dielectric layer and the overlying grid structure, such as by the methods of U.S. Pat. No. 5,302,238, issued to Fred L. Roe et al. on Apr. 12, 1994, and U.S. Pat. No. 5,372,973, issued to Trung T. Doan et al. on Dec. 13, 1994. Alternatively, a field emission array may be fabricated by forming the dielectric layer and the overlying grid structure, then disposing material over the grid structure and into openings therethrough to form the emitter tips, such as by the technique disclosed by U.S. Pat. No. 5,669,801, issued to Edward C. Lee on Sep. 23, 1997. Such conventional field emission array fabrication methods typically require the use of masks to independently define the various features, such as the column lines, resistors, and emitter tips, thereof.
Another exemplary method of fabricating field emission arrays is taught in U.S. Pat. No. 5,374,868 (hereinafter xe2x80x9cthe ""868 Patentxe2x80x9d), issued to Kevin Tjaden et al. on Dec. 20, 1994. The fabrication method of the ""868 Patent includes defining trenches in a substrate. The trenches correspond substantially to columns of pixels of the field emission array. A layer of insulative material is disposed over the substrate, including in the trenches thereof. A layer of conductive material and a layer of cathode material (e.g., polysilicon) are sequentially disposed over the layer of insulative material. A mask may then be disposed over the layer of cathode material and the emitter tips and their corresponding column lines defined through the cathode material and xe2x80x9chighly conductivexe2x80x9d material layers, respectively. The method of the ""868 Patent is, however, somewhat undesirable in that the mask thereof is not also employed to fabricate resistors, which limit high current and prevent device failure. Moreover, in the embodiment of the method of the ""868 Patent that employs a single mask to fabricate both the emitter tips and their corresponding column lines, neither the xe2x80x9chighly conductivexe2x80x9d material nor the cathode material is planarized. Thus, the layer of cathode material may have an uneven surface and the heights of the emitter tips defined therein may vary substantially. In embodiments of the method of the ""868 Patent where the layer of xe2x80x9chighly conductivexe2x80x9d material is planarized, only the emitter tips are defined through the mask.
Accordingly, there is a need for a field emission array fabrication process that employs a minimal number of masks to define emitter tips of substantially uniform height, their corresponding resistors, and their corresponding column lines.
The present invention includes a method of fabricating a field emission array, including the emitter tips, associated resistors, and column lines thereof, and field emission arrays fabricated by the method.
The method of the present invention includes disposing a layer of conductive material over a surface of a substrate. The layer of conductive material may be deposited onto the substrate in a desired thickness by known techniques. Known patterning techniques may be employed to define substantially mutually parallel conductive lines, each of which extends over the substrate, from the layer of conductive material. As the layer of conductive material is patterned, the substrate is exposed between adjacent conductive lines.
A layer of conductive material or semiconductive material, from which emitter tips and resistors may be defined, may be disposed over the exposed regions of the substrate and over the conductive lines. Thus, the layer of conductive material or semiconductive material, which is also referred to herein as an emitter tip-resistor layer, may comprise a low work function material. The layer of conductive material or semiconductive material may be planarized by known processes, such as by known chemical-mechanical planarization (xe2x80x9cCMPxe2x80x9d) techniques.
The relative thicknesses of the conductive lines and the layer of conductive material or semiconductive material preferably facilitate the exposure of at least a substantially longitudinal center portion of the conductive lines as emitter tips and their corresponding resistors are defined from the layer of conductive material or semiconductive material. Moreover, the thickness of the layer of conductive material or semiconductive material preferably facilitates the definition of emitter tips and resistors of a desired height.
The layer of conductive or semiconductive material may be patterned by known processes, such as by disposing a mask thereover and removing selected potions of the layer through apertures of the mask. As the layer of conductive material or semiconductive material is patterned, emitter tips and their corresponding resistors may be formed by employing a single mask. Thus, the emitter tips and their corresponding resistors may be defined substantially simultaneously.
Of course, the emitter tips and resistors may comprise different materials, in which case the layer of conductive material or semiconductive material would include a lower layer of resist material and an upper layer of emitter tip material. When different materials are employed to fabricate the resistors and emitter tips of the field emission array, different etchants may be required to pattern the layer of conductive material or semiconductive material.
As the emitter tips and their corresponding resistors are defined through the layer of conductive material or semiconductive material, portions of the layer of conductive material or semiconductive material over the conductive lines may also be removed. Preferably, the layer of conductive material or semiconductive material extends over at least one peripheral edge of the conductive lines. Thus, only a portion of each of the conductive lines is exposed through the layer of conductive material or semiconductive material.
The column lines of the field emission array are defined by removing at least the substantially center longitudinal portion thereof. Preferably, a substantially anisotropic etchant is employed that etches the conductive material of the conductive lines with selectivity over the material or materials from which the emitter tips and resistors are defined. Thus, when a portion of the layer of conductive material or semiconductive material extends over a peripheral edge of the conductive lines, an underlying lateral edge portion of each of the conductive lines is effectively shielded from the etchant. Preferably, both lateral edges of the conductive lines are preserved and the conductive material substantially removed therebetween to expose the substrate centrally therethrough. Thus, the lateral edges of one conductive line may each define a portion of separate, adjacent column lines.
The field emission array may then be processed as known in the art to fabricate an anodic grid structure, including row lines that are substantially electrically insulated from the column lines. The field emission array may then be assembled with other components of a field emission display, such as a display screen and housing.
Other features and advantages of the present invention will become apparent to those of ordinary skill in the art through a consideration of the ensuing description, the accompanying drawings, and the appended claims.